Read-only-memory (ROM) is a type of semiconductor memory chip that permanently stores instructions and/or data. Contrary to a read/write memory (RWM), in which data stored can be easily altered and will be lost on power shutdown, ROM is non-volatile and includes no mechanism for altering data after it is initially stored in the memory cell array. Read-only-memories have been extensively used to store control routines in personal computers (ROM BIOS), in peripheral controllers, and in plug-in cartridges such as printers, video games, etc.
When a read-only-memory is designed, the configuration of the memory cell array and the structure of the interface circuitry are designed to be compatible. Generally, a memory cell array of a given size requires a given number of address inputs which must be decoded in a predetermined manner. And if the size of the cell array is altered, the interface circuitry must be correspondingly altered. For example, a ROM having 2.sup.N addresses may require an interface circuitry that provides N address lines. If the memory capacity of the ROM is increased to 2.sup.M (M&gt;N), then a new interface circuitry providing M address lines will be required. Generally, this requirement renders the existing system unusable and a new system or a new motherboard will be required.
In order to save initial investment, it is highly desirable to provide expanded ROM memory space in existing computers (including video games, etc.). One of the most commonly used method to utilize expanded ROM capacity without substantially increasing the number of address inputs is to organize the memory array into sub-arrays, which are commonly referred to as "pages", and address them accordingly. For example, in a particular system, a ROM with 4K storage unit may require ten address inputs. Expanding the ROM capacity for the same system to 16K would then require twice (log.sub.2 4) as many address inputs, totalling 20. However, if the 16K array is organized into four separate pages, each being an individually addressable 4K array, then only two additional address inputs would be required to select the proper page. Therefore, only twelve address inputs, instead of the twenty inputs in a non-paged configuration, will be required for the expanded ROM.
Examples of the paged ROMs include page-addressed ROMs, such as Model 27513 developed by Intel Corp. The page-addressed ROMs are plug-compatible with non-paged ROMs and allow the expansion of addressable space to four times that amount. These devices, however, require that two or three of the binary data bus lines that previously delivered data only out from the ROM (read-only) be made bidirectional (i.e., read and write) in order to receive page select data. Since few computers have been constructed to provide write signals in ROM program memory, these devices have not been widely usable.
Other techniques have also been disclosed in the prior art to expand the addressable space in ROMs. U.S. Pat. No. 4,831,522 discloses a circuit and method for replacing an existing computer ROM having N binary address lines for addressing 2.sup.N addresses and receiving N system address lines with an expanded ROM having Y binary address lines (Y&gt;N) for storing information in 2.sup.Y addresses. The device disclosed in the '522 patent requires an address signal generator to generate additional binary address lines and a default page selector means for toggling the additional binary address lines between a current selected page and a default page, the default page selector means being adapted to receive the most significant of the N system address lines. This device has only very limited applications, and is applicable largely in situations in which the desired expanded ROM array is available in a like size package and with acceptable access times.
U.S. Pat. Nos. 4,744,053 and 5,231,603 disclose a variable page ROM to provide memories of increased capacity for pre-existing systems having different fixed numbers of address inputs. An appropriate page configuration is selected to accommodate the number of address inputs in the system, which is adapted to generate a page address signal having the required number of bits on the data bus. The selected page configuration is then obtained by mask programming the address decoder and input buffer circuits, and the page address signal from the data bus is routed through the data transfer buffers and stored in a RAM for use in conjunction with the row and column address inputs. The variable page ROMs disclosed in the '053 and '603 patents require that the ROM interface be capable of receiving and implementing a write-enable control signal. This is generally not available in most computers. Thus the variable page ROM devices of '053 and '603 would require substantial hardware modifications and may not be usable in most applications. Furthermore, since the correspondces between the various pages and the ROM interface are fixed, the variable page ROM devices provide only limited numbers paging configurations.
U.S. Pat. No. 4,979,148 discloses a device for increasing options in mapping ROM in computer memory space. In according to the '148 patent, the ROM code is stored in a feature card in two different versions, or two fields. An adder is provided in the address decoder with an input from the multi-bit register, which is provided in the feature card to store a numerical quantity indicating the particular segment of the read only memory space in which the ROM code of the feature card is to be mapped. The adder output is coupled to the address decoder and to addressing circuitry for the memory device storing the ROM code. The adder is arranged so as to produce an output which is the sum of unity plus the contents of the register, and the address decoder is modified so that it also responds to the output of the adder, in addition to responding to the register. Finally, the Least Significant Bit of the register to select between the two different fields in the memory device on the feature card. The device disclosed in the '148 patent does not allow the ROM capacity to be expanded.
U.S. Pat. No. 5,226,136 discloses a memory cartridge bank selecting apparatus containing a large-capacity, one-chip ROM. Storage area of the ROM is divided into a plurality of banks having respective memory addresses and one specific bank among them is allocated to an address space accessible all the time by the central processing unit. Bank selecting data for selecting other banks is stored in that specific bank. The bank selecting data is read out with execution of a program stored in the specific bank, being loaded in a counter. The content of the counter is inputted to the most significant three bits of address of the one-chip ROM. The most significant three bits of the address function as bank designating bits. An arbitrary bank of the one-chip ROM is changed over at an arbitrary timing by the bank selecting data outputted from the other banks of the one-chip ROM. Similar to many of the prior devices discussed above, the apparatus disclosed in the '136 patent requires read/write signals to select the appropriate page. Furthermore, the '136 patent requires a counter to execute the paging program stored in the specific bank.